The present invention relates to a field of electronic design automation, and more specifically, to a method and apparatus for simulating a digital circuit.
In a circuit design field, after design of a digital circuit is completed, function verification can be performed on the digital circuit through simulation, so as to determine whether it can achieve a desired function. On the other hand, the digital circuit will consume a power during its operation. For example, a complementary metal oxide semiconductor (CMOS) digital circuit will consume a power including a static power and a dynamic power during its operation. The static power includes leakage power, and the dynamic power includes a switching power and a short-circuit power, where the switching power can be further divided into a functional power and a glitch power. When a signal inputted to the digital circuit is switched between 0 and 1 in each clock cycle, the functional power will be consumed. Furthermore, when the signal is switched between 0 and 1, waveform glitches may occur at outputs of respective gate circuits in the digital circuit due to transmission delays of the respective gate circuits, thereby the glitch power is consumed. If a total power of the digital circuit consumed during its operation is too large, or the glitch power caused by, for example, the transmission delays of the gate circuits is too large, the digital circuit may not be put into practical use. Therefore, before manufacturing of the designed digital circuit, a power estimation is required to be performed on the designed digital circuit in addition to the function verification.
It is difficult to perform the power estimation on the digital circuit, and an accurate power estimation generally requires a lot of simulations. Although some vectorless power estimation methods and research tools have been proposed to estimate the power of the digital circuit, such methods and tools have limited accuracy and are only applicable to small-scale circuit designs, not industrial circuit designs. Currently, a simulation-based power estimation method is more widely used. In this method, firstly, the digital circuit is simulated and an acquired waveform is recorded, then power consumed by the digital circuit is calculated based on the waveform and switching activity information of an excitation signal for the digital circuit. In the meantime, in order to make the simulation more realistic, detailed timing information of the digital circuit, including transmission delays of gate circuits and wires, is determined by means of static timing analysis (STA) before the simulation and is stored in a file in a standard delay format (SDF) in advance, and during the simulation, the SDF file is read and the simulation is performed based on the timing information recorded in the file.
However, the simulation-based power estimation method has many disadvantages. Firstly, in this method, the function verification and the determination of the timing information are performed separately, that is to say, the timing information of the digital circuit cannot be acquired while the function verification (simulation) is being performed, which reduces efficiency of the digital circuit design. Moreover, as known in the art, there are multiple paths between respective input port and output port of the digital circuit; however, in this method, the timing information stored in the SDF file is only for a critical path (slowest signal transmission path), not for the other paths (non-critical paths), therefore, the simulation based on the SDF file actually uses inaccurate timing information so that the power cannot be accurately estimated. In particular, since an accurate estimation of the glitch power (which is often 20%-40% of the dynamic power) requires very accurate timing information, the timing information stored in the SDF file cannot meet such requirement, thus the glitch power cannot be accurately estimated.